1. Field of the Invention
The present invention relates to a driving device of a plasma display panel, and more particularly, to a driving device of a plasma display panel for performing a reset period using a ramp pulse.
2. Description of the Related Art
The plasma display panel (PDP) is a flat panel display for displaying letters or images by exciting phosphors to emit light using a gas discharge in a plasma state. The PDP has higher brightness and luminous efficiency and wider viewing angle than a liquid crystal display (LCD) and a field emission display (FED) so that PDP has been in the spotlight as a display to replace cathode ray tubes (CRTs).
The PDP is classified into a DC type and an AC type according to the pixel structure arranged in a matrix form and the waveform of a driving voltage. In the DC type all electrodes are exposed to a discharge space so that charges directly move between corresponding electrodes; however in the AC type, at least one electrode of the corresponding electrodes is covered with a dielectric so that the charges do not directly move between the corresponding electrodes.
Also, the PDP is classified into a facing discharge structure and a surface discharge structure according to the method of constructing electrodes for discharge. In the facing discharge structure an address discharge for selecting a pixel and a sustain discharge for sustaining discharge occurs between a scan electrode (e.g., positive electrode) and an address electrode (e.g., negative electrode). However, in the surface discharge structure an address discharge for selecting a pixel occurs between an address electrode and a scan electrode crossing the address electrode, and a sustain discharge for sustaining discharge occurs between a scan electrode and a sustain electrode in parallel with the scan electrode.
Referring to FIG. 1, the PDP having the above described structure displays images in gray scale in a time division driving method by dividing a unit frame into a plurality of subfields SF1 to SF6. Each of the subfields SF1 to SF6 is driven in a reset period to make the charge state of a pixel uniform, an address period A1 to A6 to accumulate wall charges on the pixels to be driven, and a sustain discharge period S1 to S6 to sustain discharge the pixels. For such a driving method, each electrode is applied with a corresponding waveform of voltage signal (e.g., a predetermined waveform).
Although FIG. 1 shows the unit frame being divided into six subfields SF1 to SF6, the number of the subfields is not limited as such, and the image quality may improve with higher number of subfields. As a result, methods of dividing the unit frame into 10 to 12 or more subfields have been studied. Furthermore, if the number of the subfields increases, false contour, an important element of image quality, of the displayed image can be reduced to improve image quality.
Meanwhile, other elements for improving the image quality and maintaining the operating margin of the PDP may also be implemented. As one method of maintaining the operating margin of the PDP, a ramp reset method is used. Referring to FIG. 2, a ramp reset is performed in a reset period PR to prepare the pixels of the PDP for low voltage address operation by allowing a large amount of wall charges to be accumulated on the walls of the pixels using weak discharge and then allowing erasing of the rest of wall charges so that only the wall charges suitable for the low voltage address operation remain on the walls of the pixels of the PDP. The ramp reset method uses a voltage signal waveform including a ramp up pulse A and a ramp down pulse B as shown in FIG. 2.
FIG. 3 shows one example of a portion of a circuit for generating the ramp pulse as shown in FIG. 2 and shows a portion of a driving circuit for generating the ramp down pulse B by using a capacitive load in order to operate a switch as constant current source.
Referring to FIG. 3, a resistor R1 is coupled between a control signal S1 input terminal and the gate of a transistor Q1, and a capacitor C1 is coupled between the gate and the drain of the transistor Q1. A capacitor Cgd represents parasitic capacitance between the gate and the drain of the transistor Q1, and a capacitor Cgs represents parasitic capacitance between the gate and the source of the transistor Q1.
As an example, when the voltage applied to the electrodes of the PDP is Vc, the voltage of the ramp pulse linearly increases with respect to a time axis so that the differential value of the voltage Vc is a constant value when the current is constant as shown in Equation 1.
                              Vc          =                                    1              C                        ⁢                          ∫                              i                ⁢                                  ⅆ                  t                                                                    ⁢                                  ⁢                                            ⅆ              Vc                                      ⅆ              t                                =                                                    1                C                            ×              i                        =            Constant                                              Equation        ⁢                                  ⁢        1            
In Equation 1, C is the capacitance of the display panel and has a constant value. Therefore, in order to generate the ramp pulse as shown in FIG. 2, the current flowed in the display panel must be constant.
Referring to FIGS. 2 and 3, in order for the transistor Q1 to be completely turned-on, the capacitor Cgs between the gate and the source of the transistor Q1 is first charged, and the capacitor Cgd between the gate and the drain is charged, using the control signal S1. Also, the capacitor Cgs is charged by the capacitor Cgd and the capacitor C1 so that the time for the voltage across the gate and the source of the transistor Q1 to exceed the threshold voltage of the transistor Q1 to completely turn on the transistor Q1 is extended by some extent. In other words, the capacitor Cgs is first charged through a path {circle around (1)} to slightly turn on the transistor Q1 so that a gate current can flow through a path {circle around (2)}. Then the capacitor Cgs starts to discharge through the formation of path {circle around (2)}, and the transistor Q1 is kept from being fully turned-on. As such, the transistor Q1 is operated as constant current source using a negative feedback effect through the paths {circle around (1)} and {circle around (2)} to generate the ramp down pulse B. The lowest voltage of the ramp down pulse B is higher than a scan voltage Vscn-l by a voltage ΔV that is the Zener voltage of a Zener diode D1
However, a conventional driving circuit for generating the ramp down pulse B as above has problems as follows.
The temperature of the PDP rises in accordance with the time during which the PDP has been in operation. When the temperature rises, the insulation characteristics of the dielectric or the protective film of the PDP deteriorate, and this can lead to leakage of the wall charges. As a result, the wall charges can move and recombine within a discharge space more easily, and this can lead to the loss of the wall charges. Accordingly, discharge condition is affected by temperature variation. Since the conventional driving circuit generates a constant ramp down pulse, it performs a normal discharge at a certain temperature, but it can perform mis-discharge at a lower temperature or a higher temperature. In other words, when the discharge starting voltage is lower at the lower temperature, over-discharge occurs, and when the discharge starting voltage is higher at the higher temperature, low-discharge occurs. If over-discharge occurs, the wall charges are excessively erased so that discharge can occur even in pixels not selected in the prior address period; and if low-discharge occurs, a significant amount of wall charges remain in pixels so that discharge error occurs when a subsequent address operation is made.